Semiconductor Memory Device Performing Redundancy Repair Based on Operation Test and Semiconductor Integrated Circuit Device Having the Same
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a system LSI on which a memory is mounted. More specifically, the invention relates to the configuration of a memory core capable of executing redundancy repair on the basis of an operation test without using a fuse device.
2. Description of the Background Art
A system LSI such as a logic merged DRAM, in which a logic such as a processor or an ASIC (Application Specific Integrated Circuit) and a dynamic random access memory (DRAM) of a mass storage capacity are integrated on the same semiconductor chip (semiconductor substrate) has been developed. In such a system LSI, the logic and the memory such as a DRAM are connected to each other via a multi-bit internal data bus of 128 to 512 bits, thereby enabling data transfer speed higher than that of a general purpose DRAM by at least one or two orders of magnitude to be realized.
The DRAM and the logic are connected to each other via an interconnection. Since the interconnection is sufficiently shorter and has a small parasitic impedance than an on-board interconnection, a large reduction in charging/discharging currents in a data bus as well as high-speed signal transfer can be realized. As compared with a method of attaching a general purpose DRAM on the outside to the logic, the number of pin terminals on the outside of the logic is smaller.
For these reasons, the system LSI such as a logic merged DRAM largely contributes to higher performances of information devices for executing processes dealing with various data such as three-dimensional graphics process and image and audio process.
In such a system LSI, an increase in capacity and an increase in the number of kinds of memory cores to be mounted are conspicuous in the stream of forming a system on a chip. On a general memory, a redundancy circuit for replacement repairing a defective memory cell with a spare memory cell is mounted to assure a good yield as a design rule becomes finer in correspondence with larger capacity and higher packing density. Similarly, such a redundancy circuit has to be mounted on a memory core which is mounted on a system LSI.
In order to execute redundancy repair, it is necessary to conduct an operation test on a memory core as a target to be tested to thereby specify a defect address corresponding to a defective memory cell from the result of the operation test. Generally, the defect address is programmed in the memory core by blowing a fuse by using a laser trimming apparatus or the like. In normal operation, an input address is compared with a defective address. When they coincide with each other, by accessing a spare memory cell in place of a regular memory cell, the redundancy repair using a redundancy circuit is conducted.
When an operation test on a memory core mounted on a system LSI is carried out via a logic unit, it is feared that a test of an operation timing margin or the like on the memory cannot be accurately performed and that a sufficient test cannot be conducted since the number of test patterns generated by the logic is limited from the viewpoint of a program capacity. What is called a direct memory access test for directly testing a memory core such as a DRAM core from the outside of a system LSI via a dedicated tester such as a memory tester is therefore conducted.
FIG. 26 is a block diagram for explaining the direct memory access test using a test interface circuit.
Referring to FIG. 26, a DRAM core 500 as a target to be tested operates in response to a command control signal inCMD and an address signal inADD which are received from a selector 504 and an operation clock DCLK received from a gate 506. The DRAM core 500 receives write data inDin and outputs read data inDout.
A test interface circuit TIC receives a test clock TST_CLK, a test command signal TST_CMD, a test address signal TST_ADD and test input data TST_Din from a memory tester as an external tester and outputs test output data TST_Dout to the memory tester.
In a manner similar to a general DRAM, each of the test input data TST_Din supplied to the test interface circuit TIC and the test output data TST_Dout outputted from the test interface circuit TIC is set to have a bit width of, for example, 8 bits. On the other hand, the bit width of the DRAM core 500 is as wide as, for example, 256 bits. The test interface circuit TIC expands the 8-bit test input data TST_Din to 256-bit write data TST_Din, selects data of 8 bits from the 256-bit test output data TST_Dout from the DRAM core and outputs the data as the test output data TST_Dout to the memory tester.
In normal operation, the gate 506 supplies a clock signal CLK which is sent from the logic unit as the operation clock DCLK to the DRAM core 500. On the other hand, in a test mode, the gate 506 supplies the test clock TST_CLK which is received from the memory tester as the operation clock DCLK to the DRAM core 500.
The test interface circuit TIC receives the test command signal TST_CMD and the test address signal TST_ADD from the memory tester at a timing synchronized with the test clock TST_CLK and outputs a test command signal TIC-CMD and a test address signal TIC-ADD. The group of signals generated by the test interface circuit TIC is supplied to the selector 504. The selector 504 also receives a logic command, a logic address and a logic data input from the logic unit.
The selector 504 operates in response to a test mode entry signal TE. The test mode entry signal TE is activated in the test mode and is inactivated in normal operation. In normal operation, therefore, the selector 504 supplies the command signal and the address signal from the logic unit as signals inCMD and inADD to the DRAM core 500. On the other hand, in the test mode, the selector 504 supplies the test command signal TIC-CMD and the test address signal TIC-ADD which are supplied from the test interface circuit TIC as the internal command signal inCMD and the address signal inADD to the DRAM core 500.
By providing such a test interface circuit TIC, an external memory tester can directly access the DRAM core 500. Consequently, the direct memory access test can be carried out. A necessary operation test on the DRAM core 500 can be therefore conducted by using a general SDRAM memory tester.
For a system LSI on which a plurality of memory cores are mounted, however, when the direct memory access test using the test interface circuit TIC as described above is adopted, the operation test for redundancy repair has to be sequentially executed on the plurality of memory cores. The number of operation tests for redundancy repair is therefore large. Since the test interface circuit has to be disposed in correspondence with each of the memory cores, it increases the chip size.
For avoiding such problems, a technique of providing a DRAM core with what is called a BIST (Built In Self Test) function so that the DRAM core itself conducts an operation test is known.
FIG. 27 is a schematic block diagram showing the configuration of a conventional DRAM core 510 having the BIST function.
Referring to FIG. 27, the DRAM core 510 comprises: a control circuit 20 which receives the command control signal CMD and the address signal ADD and controls the whole operations of the DRAM core 510; a memory cell array 30 in which memory cells are arranged in a matrix; a decoding circuit 40 for selecting a memory cell according to the address signal; a data path band 50 for amplifying data read from the memory cell and writing write data to the memory cell array 30; and an input/output buffer 60 for receiving/outputting input/output data between the DRAM core and the outside of the DRAM core.
The memory cell array 30 is divided into a plurality of memory mats MAO to MAn (n: natural number). Each memory mat is divided into a plurality of sub memory arrays by sub word driver bands SWD. In each of the sub memory arrays, sub word lines SWL and bit line pairs BLP are provided in correspondence with rows and columns of the memory cell. A memory cell row is selected hierarchically by a main word line MWL and the sub word line SWL.
A sense amplifier for amplifying data to be transmitted to the bit line pair BLP is divided into sense amplification bands SA0 to SAn+1. The sense amplification bands are provided at both ends of each memory mat. Each sense amplification band has what is called a shared sense amplification structure which is shared by neighboring memory mats.
An internal data bus pair IBP is disposed every plurality of memory cell columns so as to be shared by the memory mats. When it is assumed that each of the internal data bus pairs IBP is disposed every L memory cell columns (L: natural number), the decoding circuit 40 generates a column selection signal to perform L:1 column selection. The column selection signal is transmitted through a column selection line CSL disposed on every sense amplification band.
In each sense amplification band, each internal data bus pair IBP and a bit line pair corresponding to the selected memory cell column are coupled to each other.
The DRAM core 510 further comprises a BIST circuit 520.
The BIST circuit 520 includes: a BIST control unit 110 for controlling execution of an operation test; and an ALPG unit 120 for loading a prestored program of test patterns in accordance with an instruction of the BIST control unit 110 and generating a test pattern by arithmetic operation. The ALPG unit 120 generates a command control signal and an address signal according to the generated test pattern. In the test mode, the control circuit 20 operates the DRAM core 510 on the basis of the command control signal and the address signal generated by the ALPG unit 120.
The BIST circuit 520 further comprises a redundancy repair analyzing unit 130 for generating information for replacement repair on the basis of test data outputted from the memory cell array via the internal data bus pair IBP and the data path band 50 in the test mode.
In a conventional redundancy repair scheme, replacement repair information analyzed by the redundancy repair analyzing unit 130 at the time of the operation test is read by the memory tester or the like. Further, a fuse blowing step is provided after execution of the operation test. On the basis of the read replacement repair information, a defect address corresponding to a defective memory cell is programmed in a fuse circuit 530 in the decoding circuit 40 in a nonvolatile manner. In the fuse blowing step, a necessary fuse blowing operation is executed by a procedure of laser trimming or the like in the fuse circuit 530.
In the DRAM core 510 in which the defect address is programmed as described above, in normal operation, coincidence between the input address signal ADD and the defect address is judged. When a memory cell row or a memory cell column corresponding to the defective memory cell is selected by the address signal, a spare memory cell is accessed in place of the regular memory cell. As a result, even in the case where a defective memory cell occurs in the memory cell array, replacement repair is performed by using the spare memory cell and a normal storing operation can be performed.
As described by referring to FIGS. 26 and 27, also in the case of carrying out the. direct memory access test using the test interface circuit and the operation test based on the BIST function, the program of the failure address necessary to determine the redundancy repair is executed by blowing a fuse in the DRAM core.
FIG. 28 is a schematic block diagram showing the configuration of a conventional system LSI 550 having a DRAM core in which redundancy repair is executed by blowing a fuse.
Referring to FIG. 28, the system LSI 550 comprises a logic unit 2, the DRAM core 510 (50), a CPU (Central Processing Unit) 4, and an analog core 6 which are connected via an internal line 8. The logic unit 2 is coupled to an external terminal 555 and can receive/transmit data from/to the outside.
In the DRAM core 500 or 510, the fuse circuits 530 for determining redundancy repair are disposed. The space above the area in which the fuse circuits 530 are provided cannot be used as a chip wiring area since. a laser beam used to blow a fuse has to be passed. Consequently, gate mounting density, that is, packing density of a logic circuit constructed by an ECA (Embedded Cell Array) or the like is limited.
It is also possible to give priority on the degree of freedom in layout design and adopt a configuration in which the fuse circuits 530 are disposed concentratedly in a specific area on the system LSI 550 and signal lines are provided between the fuse circuits disposed concentratedly and each DRAM core. However, the problem of the necessity of an expensive laser trimming apparatus for trimming a fuse is not solved.
In the configuration of a system LSI on which a DRAM core of a large-scale capacity is mounted, therefore, when information necessary for redundancy repair typified by a defect address can be retained in each of the DRAM cores without using a fuse device, the redundancy repair can be executed while maintaining the degree of freedom in layout design without requiring an expensive laser trimming apparatus. Thus, the product yield can be improved.
It is an object of the invention to provide a semiconductor memory device capable of automatically executing an operation test necessary for redundancy repair on the basis of a BIST function and holding information necessary for redundancy repair into a memory core without using a fuse device, which is suited to be mounted in a system LSI in which a logic unit and a memory core are embedded.
Another object of the invention is to provide a configuration of a semiconductor integrated circuit device capable of efficiently conducting an operation test based on a BIST function necessary for redundancy repair on a plurality of memory cores.
Further another object of the invention is to provide a configuration of a semiconductor device capable of repairing a memory cell as well, which becomes defective later while suppressing the number of test items of an operation test carried out based on a BIST function. By employing a method of performing detection when the power is turned on, detection of a defect and redundancy repair on a detected defect can be efficiently executed.
The invention will be summarized as follows. The invention relates to a semiconductor memory for inputting/outputting data in accordance with an input address, comprising a memory cell array, a self test circuit, and a decoding circuit. The memory cell array stores data by a plurality of regular memory cells and spare memory cells. The self test circuit conducts an operation test on the memory cell array to detect a defective memory cell. The self test circuit includes: a self test control unit for activating the operation test at predetermined time; and a redundancy repair analyzing unit for analyzing data outputted from the memory cell array in the operation test and outputting a plurality of redundancy code signals for indicating a defect address corresponding to the defective memory cell. The decoding circuit selects a memory cell to which the data input and output is performed in accordance with the input address. The decoding circuit includes a repair determining circuit for instructing an access to the spare memory cell when the input address and the defect address coincide with each other. The repair determining circuit has a plurality of redundancy code holding circuits provided in correspondence with the plurality of redundancy code signals. Each of the plurality of redundancy code holding circuits takes in a signal level of corresponding one of the plurality of redundancy code signals outputted from the redundancy repair analyzing unit at the time of conducting the operation test and holds the received signal level.
Therefore, the main advantage of the invention is that the operation test for detecting a defective memory cell can be automatically executed on the basis of the BIST function and the defect address corresponding to the defective memory cell can be stored without using a fuse device. As a result, the restriction on layout in the wiring area on the chip is lessened and the degree of freedom in layout is improved.
According to another aspect of the invention, there is provided a semiconductor integrated circuit device comprising a plurality of memory cores, a self test circuit, a selection control circuit and a selector circuit.
Each of the plurality of memory cores executes data input and output according to an input address. Each of the plurality of memory cores includes: a memory cell array for storing data by a plurality of regular memory cells and a spare memory cell used to be replaced with a defective memory cell detected at the time of an operation test; and a decoding circuit for selecting a memory cell as a target of the data input and output in accordance with the input address. The decoding circuit includes a repair determining circuit for instructing an access to the spare memory cell when the input address and a defect address corresponding to the defective memory cell coincide with each other. The repair determining circuit has a plurality of redundancy code holding circuits provided in correspondence with a plurality of redundancy code signals for indicating the defect address. Each of the plurality of redundancy code holding circuits takes in a signal level of a corresponding one of the plurality of redundancy code signals at the time of the operation test and holds the taken signal level. The self test circuit is shared by the plurality of memory cores and conducts the operation test on the memory cell array to detect a defective memory cell. The self test circuit includes: a self test control unit for activating the operation test; and a redundancy repair analyzing unit for analyzing data outputted from the memory cell array in the operation test and outputting a plurality of redundancy code signals. The selection control circuit selects one of the plurality of memory cores. The selector circuit is disposed between the plurality of memory cores and the self test circuit and couples the one of the memory cores and the self test circuit in accordance with selection by the selection control circuit.
The self test circuit for conducting the operation test for detecting a defective memory cell on the basis of the BIST function is shared by the plurality of memory cores, and the defect address corresponding to a defective memory cell can be stored in each of the memory cores without using fuse devices. As a result, the reduction in layout area and the lessening of the restriction regarding layout of the wiring area on the chip are realized, so that the degree of freedom in layout design is improved.
According to further another aspect of the invention, there is provided a semiconductor memory device for inputting/outputting data in accordance with an input address, comprising a memory cell, a program unit, a self test circuit, a control unit, and a decoding circuit. The memory cell array stores data by a plurality of regular memory cells and a plurality of spare memory units. The program unit stores, in a non-volatile manner, redundancy information for indicating an address of a defect corresponding to a preliminarily detected defective memory cell. The self test circuit for conducting an operation test to detect a defective memory cell to the memory cell array. The self test circuit includes a self test control unit for activating the operation test at predetermined time, and a redundancy repair analyzing unit for analyzing data outputted from the memory cell array in the operation test and outputting redundancy information for indicating a defect address corresponding to a defective memory cell detected by the operation test. The control unit instructs each of the program unit and the redundancy repair analyzing unit to output the redundancy information. The decoding circuit selects a memory cell as a target of the data input and output in accordance with the input address. The decoding circuit includes a plurality of repair determining circuits provided for the plurality of spare memory units. Each of the plurality of repair determining circuits stores one of the plural redundancy information outputted from the program unit and the redundancy repair analyzing unit and instructs an access to a corresponding one of the plurality of spare memory units when the defect address corresponding to the redundancy information stored coincides with the input address.
Therefore, the redundancy repair is performed on the basis of both of information stored in the program unit, for repairing a preliminarily detected defective memory cell, and information for repairing a defective memory cell detected by an operation test conducted on the basis of a BIST function. Thus, a defective memory cell which occurs later can be also repaired while suppressing the number of test items of an operation test conducted on the basis of the BIST function.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the acco anying drawings.